University of Twente Student Theses


Connecting Æthereal to the Montium

Jongsma, T.M. (2010) Connecting Æthereal to the Montium.

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Abstract:A Communication and Con�guration Unit (CCU) is developed to make it possible to connect a Montium Tile Processor (TP) to an �thereal Network-on- Chip (NoC). The CCU is the interface between the Montium TP and the NoC. A system with MicroBlaze processors connected to �thereal with a Device Transaction Level (DTL) interface is already available. For better performance for Digital Signal Processing (DSP) the system will be extended with Montium TPs. The Montium TP is a coarse-grained recon�gurable processor. In �thereal can be chosen from 2 types of Network Interfaces: bus or streaming. The only bus protocol used within this project is DTL. The implemented CCU has two interfaces to the NoC: a streaming interface for the data processing and a Memory-Mapped Input-Output (MMIO) interface for con�guration and Direct Memory Access (DMA), which can be streaming or DTL. The choice for streaming or DTL is done at design-time, because it is implemented as an optional adapter which converts DTL to streaming. To be able to test the implemented CCU on an Field Programmable Gate Array (FPGA) evaluation board, a system consisting of 2 MicroBlaze Cores and 2 Montium TPs connected to �thereal is generated. A small application is successfully executed on a Xilinx ML605 evaluation board, which contains a Virtex-6 FPGA. In this setup the Montium can run on 14.82 MHz. To be able to make a comparison with other CCUs, the design of the CCU, DTL adapter and Montium TP is also synthesized for an Application Speci�c Integrated Circuit (ASIC). The size of the CCU is 0.01478 mm2 without DTL adapter. The DTL adapter is 0.00149 mm2. These results were obtained using a 90 nm low power library and a clock frequency contraint of 400 MHz.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
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