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Analysis and design of a low power ADC

Peters, V. (2012) Analysis and design of a low power ADC.

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Abstract:The main goal of this thesis is to design an ADC for the use in a low power spectrum analyzer (SA) aiming for cognitive radio applications. The receiver of the SA should operate power efficient because of the intended use in mobile applications. It should also have a high SFDR to detect weak signals in the spectrum. For the power efficiency, a successive approximation ADC is implemented using a charge redistribution DAC. To reduce the overall power consumption of the SA, an amplification step in the signal path of the SA receiver is eliminated by creating a small input range for the ADC. This small input range introduced offset problems for which a new calibration procedure is developed. The calibration reduces the offset to under 1 LSB. The SA uses digital cross-correlation to filter noise digitally and acquire a high SFDR. Because of this the primary focus on the design of the SA and its ADC is a high linearity to prevent harmonics and inter-modulation products in the output, limiting the SFDR. The linearity of the ADC is mainly influenced by mismatch between capacitors in the charge redistribution DAC. A new calibration architecture and procedure is introduced to increase the matching of the capacitors in the DAC. The result is a 7-bit ADC consuming only 38.2 μW at 40 MS/s having a supply voltage of 1 V. The input range is 63 mV and it has a SFDR of 72 dB. With the new calibration method a higher SFDR can be achieved at the cost of a slight increase in power consumption.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
Link to this item:http://purl.utwente.nl/essays/69772
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