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Hardware accelerator sharing within an MPSOC with a connectionless NOC

Wevers, Gerben (2014) Hardware accelerator sharing within an MPSOC with a connectionless NOC.

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Abstract:For the last decades, increasing the computational performance of a microprocessor chip was mainly achieved by scaling transistor sizes. Not only can more transistors be placed in a single die, smaller transistors allow higher clock frequencies. While transistor sizes are still decreasing, designers are facing mayor power consumption issues which prevent further performance improvements by simply increasing clock frequencies. A clear trend is visible where multiple cores are added to the same chip to form so-called multi-core systems. The same trend is visible in the embedded systems domain where System-on- Chips (SoCs) are transformed into Multi-Processor System-on-Chips (MPSoCs). An MPSoC can either be homogeneous (consisting of identical processing elements) or heterogeneous (consisting of different types of processing elements, e.g. Central Processing Units (CPUs) and weakly programmable hardware accelerators). Communication between the processing elements is taking place via a Network-on-Chip (NoC). At the University of Twente multiple researchers are working on an MPSoC called Starburst. The main characteristics of this platform are: (1) the Starburst platform is a scalable distributed shared memory many-core system, (2) it targets real-time streaming applications where firm real-time requirements are assumed and (3) the set of applications to be run on the platform (and thus the communication pattern) is unknown at design time, which requires the platform to be exible. The Starburst platform was originally designed as a homogeneous MPSoC consisting of multiple identical soft-core CPUs. As a case study a Phase Alternating Line (PAL) video decoding application was mapped onto the platform. The demonstrator produced a video quality far from commercially acceptable and for some operations multiple parallel executing CPUs were required. This case study showed that the computational power was simply limited by the performance of the CPUs in the system. In order to improve the computational performance of the Starburst platform weakly programmable hardware accelerators were added, which transformed Starburst from a homogeneous MPSoC to a heterogeneous MPSoC. A problem of this approach is the fact that a hardware accelerator can only process a single data stream. In order to process multiple data streams, multiple physical copies of this hardware accelerator have to be added to the platform. This thesis focussed on techniques to share hardware accelerators across multiple data streams, as it was expected that one shareable hardware accelerator has a lower area footprint than multiple unshared accelerators. Additionally, the platform is becoming more exible in the sense that more applications are able to execute on the same platform. We solved this problem by implementing a centralized component called a gateway. The gateway is used to buffer multiple incoming data streams, and to push packets of data at high speed sequentially through the accelerators. Most accelerators have a configuration and/or state. Context switches are applied where the configuration and state for a certain data stream is loaded into the accelerator and extracted after a specific number of samples have been processed. A data ow model of the sharing mechanism is constructed, which allows us to give real-time guarantees such as latency and throughput. A case study was carried out which focussed on the audio part of the PAL signal. As this signal contains a stereo audio signal, we have used the hardware accelerator sharing mechanism to decode the left and right audio stream on the same set of accelerators, where a continuous (real-time) audio signal is produced.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
Link to this item:http://purl.utwente.nl/essays/71645
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