University of Twente Student Theses
A Charge Biased Delay Element
Marnette, Thijs (2017) A Charge Biased Delay Element.
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| Abstract: | In most modern electronic devices a wireless transmission link is available. The RF power amplfier(RFPA) of the transmitting part is a dominant source of power dissipations. To increase the efficiency of the RFPA, class E amplifiers are used. These amplifiers are prone to process, voltage, temperature and environmental changes. In self-healing RF amplifiers, the RFPA is characterized to obtain information about its performance after production and during operation. The information obtained by the characterization system is used to tune the RFPA in such way that it becomes more robust. To characterize the RFPA, the output is sampled at 8 equidistant phases of its operating frequency. These phases are obtained by a delay locked loop(DLL) driven by the local oscillator(LO) used by the up-conversion mixer preceding the RFPA. The DLL plays an essential role in the accuracy and power consumption of the characterization system. Especially jitter on the outputs of the DLL is an important contributor of inaccuracy in the measurement system. This master assignment focusses on delay elements within the DLL. An overview and a comparison is given for conventional delay elements for the specified speed, power and jitter. These specification are directly linked to the accuracy and power consumption of the PA characterization system. Furthermore, the application of charge biasing in delay element is investigated with the objective to reduce power dissipation in the voltage controlled delay line. A charge biased delay element is proposed for which an analytic model is derived to obtain insight in power consumption, speed and jitter. With the model is shown that compared to the current starved inverter, the charge biased delay element consumes less power, but has a considerable increase in jitter and delay time. Escpecially for large delay times the jitter of the charge biased delay element becomes orders of magnitude larger than the conventional delay element. An analysis is done on the optimal number of cascaded delay elements for power and jitter performance to obtain a certain delay. From the analysis could be concluded that more delay elements results in better jitter and power performance. This conclusion excludes delay elements that dissipate static power. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering MSc (60353) |
| Link to this item: | https://purl.utwente.nl/essays/74210 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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