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Design of an Energy Efficient 12-bit 100MS/s SAR ADC in 22nm FD-SOI

Vree, J.H. de (2017) Design of an Energy Efficient 12-bit 100MS/s SAR ADC in 22nm FD-SOI.

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Abstract:Current state-of-the-art high-frequency SAR ADCs challenge the technological limits of CMOS. The focus of this thesis is on the design of analog sub-circuits of such a state-of-the-art SAR ADC in 22nm FD-SOI. The target SAR ADC has a 12-bit resolution at a sample frequency of 100Ms/s. The parasitic effects in a charge-redistributing digital-to-analog converter are modelled, and a custom unit-cell capacitor is made that minimizes the effect of parasitics. A fully differential 12-bit DAC with 4-bit thermometer code is made, consuming 969fJ per conversion. A dynamic bias comparator is implemented. Simulations of the comparator show an average energy consumption of 58fJ per comparison and 145µV input-referred noise. A track and hold circuit, that utilizes the absence of latch-up and smaller parasitic capacitance in the FD-SOI technology, is implemented with a SINAD of 74.35dB and a very low energy consumption of 15fJ per conversion. The energy consumption for the full 12-bit SAR ADC is estimated to be 2.3pJ per conversion.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:50 technical science in general, 53 electrotechnology
Programme:Embedded Systems MSc (60331)
Link to this item:http://purl.utwente.nl/essays/74334
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