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Approximate multipliers for MAC

Verstoep, Bart (2018) Approximate multipliers for MAC.

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Abstract:Approximate computing techniques reduce the cost (in terms of among others area and power consumption) of computing units in exchange for a reduced accuracy. These techniques are not optimized for Multiply-Accumulate (MAC) processing elements. This leaves a lot of room for improvement as the integrator part of a MAC allows for error balancing. In this work, designs for an 8×8 bit MAC are sought that have optimal quality compared to their area cost for FPGA. To achieve this, different error balancing techniques are considered and combined with existing approximate computing techniques. An algorithm is proposed to perform an exhaustive search for the optimal designs, using an error balancing technique within a multiplier to achieve an average error close to 0. The designs found by the algorithm have a much higher quality compared to conventional approximate computing techniques for a small increase in area on the FPGA and the overall quality-cost tradeoff is improved.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Electrical Engineering BSc (56953)
Link to this item:http://purl.utwente.nl/essays/75303
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