University of Twente Student Theses

Login

Analysis and Design of a Dependability Manager for Self-Aware System-on-Chips

Geerlings, S.A. (2018) Analysis and Design of a Dependability Manager for Self-Aware System-on-Chips.

[img] PDF
6MB
Abstract:The Dependability Manager (DM) is a coprocessor for SoCs that employs reconfigurable scan networks (RSN) to increase the dependability of the chip. The DM features a novel Retargeting Engine and Interrupt Management Unit to access IEEE 1687 (IJTAG) RSNs. A toolchain was developed to integrate PDL procedures into the dependability application. The architecture was proven in simulations and on a Cyclone IV FPGA.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:https://purl.utwente.nl/essays/76229
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page