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Implementation of a power-efficient DFT based demodulator for BFSK

Meciani, Giovanni (2018) Implementation of a power-efficient DFT based demodulator for BFSK.

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Abstract:In wireless communication, the frequency offset is a problem that hinders the communication. It arises from the discrepancy between the frequencies of the oscillator of the transmitter and the one of the receiver. To solve this problem, oscillators with high frequency stability can be employed, at the expense of higher power requirements. As a consequence, this solution can be problematic in Wireless Sensors Network (WSN), where sensor nodes have limited power resources. Another solution is to correct the frequency offset within the demodulation algorithm, thus making it possible to use less power-hungry oscillators. This thesis focuses on the hardware implementation of an existing offset tolerant demodulation algorithm for BFSK modulation. Particular attention was posed in making the demodulator as power efficient as possible, given its usage in a WSN. To reach this goal, the two Discrete Fourier Transforms were optimised for zero-padding, which is an operation used in the algorithm. These two modifications allowed to save power when compared with the standard radix-2 FFT. Fixed-point is the chosen data representation. As the word length of the representation is a critical aspect that affects power consumption, an appropriate size was determined by using a procedure that makes use of MATLAB. The complete demodulator is implemented in VHDL and is used to characterise the system, when an FPGA is used in the synthesis process. Relevant results analysed are bit error ratio (BER) with different levels of noise, power consumption with different clock speeds, and resource usage.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:http://purl.utwente.nl/essays/76996
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