Comparison of divide-by 2 circuits for clocks used in mixers

Many mixers in radio receivers use quadrature mixers with 25% duty cycle clock inputs with ideally no overlap. Two clock generation circuits capable of making these desired clock inputs used within the IC-Design group can be split up in 3 stages which are shown below:  Amplification and clipping stage  Divider stage  25% duty cycle stage The purpose of this thesis is to compare the two divider stages of both implementations. These two dividers can be distinguished based on their implementation. One is called the static divider and the other is called the dynamic divider. The names come from the use of either static or dynamic latches. One circuit is a flip-flop with static latches and the other one uses a shift register with dynamic latches. The dividers are designed for certain objectives such as operating frequency range, power consumption and phase noise. Due to time limitations only power consumption and operating frequency range are discussed. The circuits are used in RF front-ends so they have to meet certain boundary conditions. The boundary conditions for the clock generation circuit are set so that the output signals have to be full swing and the duty cycle has to be between 23% and 26%. Circuit theory is used to analyse the circuits. To determine the power consumption of a circuit the load capacitance has to be known. The MOSFET capacitance model is used to determine the in- and output capacitances of the circuits. Adding the inand output capacitances of the circuits will end up in the load capacitance of a stage. Because these implementations behave differently a comparison method has to be developed. First the amplification/clipping stage should be the same such that only the input capacitance of the divider is influencing the load of the amplification/clipping stage. Also the 25% duty cycle stage should have the same input capacitance. This will cause the divider to always have the same load capacitance. The load capacitance is determined by splitting up the circuit into multiple smaller circuits. It’s determined that the dynamic divider has a bigger input capacitance than the static divider which means that it is a bigger load capacitance for the amplification/ clipping stage demanding for more power from the source. Also the output capacitance of the dynamic divider is bigger such that it has to charge more load capacitance. This means that the dynamic divider has more power consumption in the circuit. The power consumption of the stages is also simulated and verifies the found conclusions. The ratio found for the load capacitances between the circuits only differs less than 8% from the power consumption ratio. Also operating output frequency range is compared using the boundary conditions. Where the static divider consumes less power it will only work to 6.5 GHz where the dynamic divider implementation works up to 10GHz.