University of Twente Student Theses


Framework for Fine-Grained Partial Reconfiguration on FPGAs

Hogenkamp, Tom (2019) Framework for Fine-Grained Partial Reconfiguration on FPGAs.

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Abstract:Dynamic partial reconfiguration (DPR) on field-programmable gate arrays (FPGAs) allows us to reduce the power, area and increase the speed of a digital system by changing only a part of the FPGA fabric during run-time. Usually, in applications with DPR, we separate the FPGA fabric into two areas: a region that contains the parts of a design that requires to be operational the whole time (static) and a region that includes the parts of the design that are used mutually exclusively and can share the same FPGA resources at different predefined times (partial). One of the main limitations of the development tools from the two leading FPGA vendors, Xilinx and Intel, is that only one functional block (module) can be configured in the partial area at the same time. Consequently, often, many resources remain unused in the partial region if we have modules with considerable different resource requirements. Furthermore, the whole partial area is being reconfigured, despite the size of the module. Therefore, the time to reconfigure a small functional block takes the same amount of time in comparison to a large module. In this work, we introduce a framework that enables us to build applications with DPR that overcome the limitations of the vendor tools. We split the partial area into two-dimensional slots, where multiple functional blocks can be configured, and the modules take up the number of slots according to their resource requirement. Furthermore, we only have to reconfigure the slots that are occupied by the functional blocks. As a result, we do not reconfigure the complete partial area anymore, and therefore, the reconfiguration time is less.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Embedded Systems MSc (60331)
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