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FPGA partial reconfiguration and automatic variant generation as a side-channel attack countermeasure with functional HDL Clash

Westerveld, J.P. van (2020) FPGA partial reconfiguration and automatic variant generation as a side-channel attack countermeasure with functional HDL Clash.

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Abstract:This thesis proposes the automatic variant derivation of given hardware architectures using functional HDL Clash. The purpose of those variants is implementation diversity, which would involve their alternated use to introduce temporal jitter as a side-channel attack countermeasure. One systematic derivation approach involving left-fold higher-order functions is worked out as a proof of concept. Through traversal of the abstract syntax tree representation of hardware designs, it could be applied wherever possible in the MixColumns step of an AES cipher implementation. This fully automatic compile-time application yielded over 50000 variants, their suitability for impeding side-channel attacks in is yet to be verified. Additionally, the core components needed to realize a Clash FPGA design featuring partial dynamic self-reconfiguration are identified and implemented. A design element representative of a reconfigurable region is defined to have different compilation and simulation behaviour. It compiles to the HDL sources needed by FPGA EDA tools to enable partial reconfiguration, and it simulates - like on an actual FPGA - the exchange of modules. In combination with a novel partial reconfiguration controller design, simulation and measurements from a Xilinx FPGA were shown to be true to each other.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:50 technical science in general, 54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:http://purl.utwente.nl/essays/85411
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