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Automatically map an algorithmic description to reconfigurable hardware using the Decoupled Access-Execute architecture

Griët, D.D. (2021) Automatically map an algorithmic description to reconfigurable hardware using the Decoupled Access-Execute architecture.

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Abstract:This thesis proposes a framework that automatically transforms the structure of an algorithm written in the C/C++ programming language to the Decoupled Access-Execute architecture. The use of the DAE architecture creates separation of concerns. As the memory accessing and memory address calculation logic is moved into dedicated units that operates independently of other units, the computational part has access to memory only via the dedicated memory accessing units. The framework is evaluated against a subset of the algorithms provided by the MachSuite benchmark. The runtime of the algorithm is measured then it is transformed into the DAE architecture and the appropriate high-level synthesis directives are automatically added and again the runtime is measured. Depending on the benchmark a maximum speedup of 1.63x is observed while in the worst case a negligible speedup is observed, showing that the transformation highly depends on the algorithm. In addition to runtime measurement, power and area usage is also measured. Power usage appears to be directly linked to the speedup: The power usage is increased for the algorithms where the speedup also is increased. The amount of area used for the transformed algorithm also increases for those.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:https://purl.utwente.nl/essays/88737
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