University of Twente Student Theses


Low power ASIC design of a DDPSK demodulator

Dijkshoorn, P.C. (2021) Low power ASIC design of a DDPSK demodulator.

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Abstract:While Ultra-Narrowband communication can be used in Internet of Things and Wireless sensor networks for low data rate applications they heavily suffer from frequency offset. To overcome the impact of a frequency offset in these applications, a frequency offset tolerant demodulation and detection scheme can be used called Double Differential Phase-Shift Keying (DDPSK). For this purpose, a DDPSK demodulator is implemented using VHDL and synthesized towards ASIC. Digital signal processing components prior to the demodulator including a baseband converter, CIC filter and FIR filter are implemented as well. The demodulator uses BPSK and is designed to be power efficient. Suitable power saving techniques will be found and applied. Moreover, trade-offs such as power consumption versus data precision are investigated. Given the low data-rate of the application, one possible solution in case of leakage power dominance is duty cycling the digital processing. Store samples while the processing part is powered off and do the processing in higher clock frequencies afterwards. This leads to another trade-off: how large should the memory be for storing samples and how fast should they be processed afterwards.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:50 technical science in general
Programme:Embedded Systems MSc (60331)
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