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Reliability analysis of Triple Modular Redundancy

Nowee, Stijn (2022) Reliability analysis of Triple Modular Redundancy.

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Abstract:In this paper the effect of a Triple Modular Redundancy(TMR) implementation on the reliability of a system is examined. To accomplish this, a micro-processor with a RISC-V architecture has been simulated with and without the TMR implementation. In the simulation are both Single Event Transients(SET) and Multiple Event Transients(MET) injected. Additionally, a transistor fault has been simulated with the TMR implementation. The TMR is applied to the Multi/Div block of the processor and the faults will be injected at the input of these triplicated blocks. The performance of the systems with and without TMR will be compared using the ratio of the number of faults injected to the number of faults propagated. When the system is only injected with SET’s, the system without TMR has a ratio from 0.058 to 0.389 depending on the probability of a SET occurring, while the system with TMR does not propagate any fault at all. If MET’s are injected the system without TMR performs better with a ratio between 0.069 and 0.291, while the system with TMR has a ratio between 0 and 0.036. The TMR implementation reduces the probability of an error propagating significantly, but if a Multiple Event Transient hits multiple similar wires, it can still fail. To combat this other forms of redundancy should be implemented.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Electrical Engineering BSc (56953)
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