University of Twente Student Theses
Design of an FPGA based PLL system
Wisselink, N. (2022) Design of an FPGA based PLL system.
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| Abstract: | In this report a fast-acting grid-tied Phase-locked loop system (PLL), implemented on a field programmable gate array (FPGA), developed using a model-based approach in Simulink is discussed. The system is part of an inrush current mitigation project, which aims to mitigate inrush currents and other transients using a gallium nitride based inverter. A phase-locked loop is required for synchronization to the grid and error-calculation. This system was designed, simulations were performed and hardware tests were conducted. After which was concluded that the system was operating correctly. The PLL system was integrated with the error controller, after verification the system was confirmed to operate correctly. |
| Item Type: | Essay (Bachelor) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 50 technical science in general, 53 electrotechnology |
| Programme: | Electrical Engineering BSc (56953) |
| Link to this item: | https://purl.utwente.nl/essays/92318 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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