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Comparison between logic families for multiphase clocking applications

Dharmasena, N.B.C (2022) Comparison between logic families for multiphase clocking applications.

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Abstract:IoT technology has created a need for low power consumption and high selectivity resulting from low phase noise. The Windmill frequency divider is a circuit that takes two input clocks, LO+ and LO- that are at 50% duty cycle and produces four 25% duty cycle signals with half the frequency of input clocks and having non-overlapping phases. The windmill circuit is currently implemented using CMOS 22nm NOR gates; thus, this paper investigates the design of the exact windmill circuit but now also using a different logic family class namely PFSCL (positive feedback source coupled logic). The two families of NOR gates are then designed to have the same operating speed of 6Ghz 10ps rise/fall time to have a fair comparison of power dissipation and phase noise. After that the CMOS NOR gate’s maximum operational speed was found to be 40Ghz at 3ps rise/fall time. The PFSCL NOR was then designed to operate at this max operational speed by scaling. The phase noise and power dissipation were then plotted vs the input frequency for both logic families at 40Ghz and at 5 other frequencies below that to compare the behavior of CMOS and PFSCL NOR. In the end, it was then determined that phase noise performance of the PFSCL was not too different compared to CMOS. However, PFSCL NOR dissipated 15.6 times more power than the CMOS NOR gate while keeping their speeds the same. The different family NOR gates were then used to construct entire Windmill circuits. The circuits were simulated using Cadence Virtuoso.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Programme:Electrical Engineering BSc (56953)
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