University of Twente Student Theses
Side channel pattern matching using neural networks on FPGA
Balaji, R. (2022) Side channel pattern matching using neural networks on FPGA.
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| Abstract: | Embedded hardware devices like smart cards are prone to threats either due to leakage of information (on a side channel) which could be further analysed to extract important information or it can also be through manipulation of the device functioning by injecting fault from external sources (fault injection attack). Therefore, it is important to develop countermeasures against these threats which require testing using similar attack scenarios. In the context of Side channel analysis and fault injection attacks, a precise triggering device is required to enable the side channel device on the host. While an oscilloscope can achieve this triggering on a selected region of signal, there are certain limitations like existence of random delays/noise in the signal and unnecessarily large measurement windows. For this reason, Riscure has developed an FPGA based triggering device to detect a specific desired reference pattern in the side channel trace and send a trigger signal back to the device under attack/analysis. While the existing design makes use of a Sum of Absolute Differences (SAD) algorithm for the pattern detection, there is scope for improving this pattern matching performance further by reducing number of false positives and negatives and improve latency and resource performance on the FPGA. In recent years, inference of Neural networks on an FPGA has gained popularity and specifically there many instances of low latency inference of such Neural Networks. This project aims to explore the possibility of replacing existing traditional methods and using Neural Networks instead to achieve improved pattern matching results while maintaining similar latency and resource usage targets. Specifically, this project explores low latency inference of Neural Networks on FPGAs. In this thesis, an Multi Layer Perceptron (MLP) is trained with a data-set comprising of a number of side channel traces of which each trace having the occurrence of a selected reference pattern to be detected. Once a network is designed which capable of detecting desired pattern on these side channel traces accurately, further techniques of optimizing the network such that it is feasible for FPGA inference while maintaining low latency and resource constraints are explored. Here, quantization aware training and fixed point design play an important role to achieve FPGA inference with minimal accuracy drop. A design is finalized after experimentation such that it is applicable on various patterns/sizes. This design is then tested on various levels from software testing to RTL simulations to assess the performance on a Xilinx Kintex 7 series FPGA which is the core of the icWaves device. The resulting design achieves a latency of around 430 ns, allows for a maximum size pattern of around 310 samples while running at a maximum clock frequency of 230 Mhz and reports high accuracy. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Embedded Systems MSc (60331) |
| Link to this item: | https://purl.utwente.nl/essays/93831 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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