University of Twente Student Theses


Emulation of Analog Mixed-Signal Circuits on an FPGA

Sulzer, Niels (2022) Emulation of Analog Mixed-Signal Circuits on an FPGA.

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Abstract:Verifying analog mixed-signal (AMS) designs with conventional methods has the downsides of being expensive – in the case of hardware-in-the-loop (HIL) verification – or tedious – in the case of analog and digital co-simulation. Another verification technique is explored in this thesis: emulation using field-programmable gate arrays (FPGAs). Analog designs are modelled in synthesizable register transfer level (RTL) which can be run on an FPGA, sacrificing accuracy for faster run times. Based on the tools svreal, msdsl and anasymod developed at Stanford, analog designs are modelled in Python using various techniques, and hardware description language (HDL) descriptions are generated. This process is applied to a first-order and second-order audio continuous-time sigma-delta (CTΣ∆) converter. Emulation shows near identical performance to Simulink models. The existing tool is also extended to allow sweeping analog model parameters during emulation, opening the use of emulation for analog design-space exploration. A standalone FPGA demo is built on a Xilinx XC7Z020 platform, with an emulated CTΣ∆ analog to digital converter (ADC) with the ability to change model parameters, in a real-time audio application. The design takes less than 6% of the available FPGA resources. Analog emulation is shown to be a feasible technique for this use-case, given that longer emulation times can be achieved in the future.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
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