University of Twente Student Theses


Area-Optimized RISC-V-Based Control System for 22nm FDSOI Analog and Mixed-Signal Test Chips

Kruiper, T.R. (2023) Area-Optimized RISC-V-Based Control System for 22nm FDSOI Analog and Mixed-Signal Test Chips.

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Abstract:This paper presents the work on a RISC-V control system labeled UTRISCY. This design is an area-optimized, modular and reusable system designed for on-chip control to accelerate the testing by the ICD group on analog and mixed-signal CMOS designs. The system consists of several building blocks that communicate using standard bus interfaces, and can be configured to use one or two memory components depending on the performance needs. A comprehensive search for open-source RISC-V cores has been done, and the open-source SCR1 core is shown to be the most suitable for use in this system. A standard JTAG interface allows a debug probe connected to a host PC to program the memories of the UTRISCY control system, while also providing general communication capabilities. A voltage-controlled oscillator, the calibration of which is performed by UTRISCY, has been used as a typical use case. To verify the system, a comprehensive verification setup is provided that simulates the complete system, including the emulation of a connected debug probe using the OpenOCD debugger. Finally, the several components of the UTRISCY control system have been synthesized and placed-and-routed for the Globalfoundries’ 22nm FDSOI technology (22FDX), which results in an area usage of 57283µm2 including six bondpads, and two 4KB memories, with a maximum operating frequency of 156MHZ at 0.8V. It has been shown that this area can be reduced to 36710µm2 by using the smallest configuration of the SCR1 core and only including a single 2KB memory.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Electrical Engineering MSc (60353)
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