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Low-Latency GFSK Demodulation Architecture Comparison and Design for FPGA

Lopez, A. (2023) Low-Latency GFSK Demodulation Architecture Comparison and Design for FPGA.

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Abstract:Gaussian Frequency Shift Keying (GFSK) is a widely used type of continuous phase modulation (CPM), where a Gaussian pulse shaping filter is used before frequency modulation. Commercially available GFSK demodulators are mostly optimised to minimise power consumption or bit error rate (BER), but rarely consider the latency of demodulation. However, in situations where the output of the demodulator is used in a feedback loop, the demodulator’s latency is a crucial factor regarding stability of the system. In this paper, we primarily investigate which noncoherent GFSK demodulator architecture, suitable for implementation on a field-programmable gate array (FPGA), has the lowest latency of demodulated bits, while considering BER performance secondary. Three demodulation methods were modelled in Simulink: instantaneous frequency estimation using zero-crossing detection, a quadricorrelator, and matched filters with envelope detection. Simulation results show the quadricorrelator demodulator is most suitable, introducing a latency of 1 μs and a BER of 0.1% at EbN0 = 13.2 dB. The realistic model of this demodulator for FPGA produces a BER of 0.1% with EbN0 = 14.6 dB.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering BSc (56953)
Link to this item:https://purl.utwente.nl/essays/96205
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