University of Twente Student Theses
An Energy-Efficient Correlator Architecture design for FPGA.
Jauregui Morris, R.A. (2024) An Energy-Efficient Correlator Architecture design for FPGA.
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| Abstract: | In radio astronomy, large radio telescopes use multiple fields of antennas around the Earth to capture waveforms in the sky for astronomical measurement and imaging. The significance of the correlator in the telescopes is to extract useful information from multiple pairs of antennas in one field and between fields for a higher resolution of the imaging. Therefore, it usually tends to be computationally expensive due to its quadratic growth relative to the number of pairs of antennas in a two-dimensional grid, the number of bands, and frequency channels. The SKA correlator with more than one hundred thousand antennas is predicted to consume in the Mega-Watts range. Assuming power demand grows in proportion to the computational intensity, the power demand of the correlator will grow quadratically as well. Different techniques were presented for optimizing the correlator performance in speed and area. Approximate computing has been one of the techniques to reduce the power budget of high computational expenses. In recent studies, a set of approximate multipliers was employed in the core of the correlators to investigate the quality performance and the reduction of the power demand. A 19% power reduction was achieved by doing so with Application Specific Integrated Circuit (ASIC). However, these types of approximate multipliers are only optimal on ASIC technology and will lack performance on a Field Programmable Gate Array (FPGA) device, due to their architectural differences. This paper presents a methodology for building a correlator architecture from an algebraic description. A set of power Pareto-Optimal 8-bit input approximate multipliers designed for ASIC and FPGA implementation are investigated for their performances concerning the correlator's output-quality for image processing, the number of LUTs savings, and power savings improvement on an FPGA device. For SNR levels at the input (SNR_{in}) of the correlators up to 30 dB, the highest core dynamic power savings achieved by using the approximate multipliers in this paper is 26.56% (see Table 8). However, as the number of antennas increases quadratically for correlation, this power savings decay to 2.9%. For this approximate multiplier, an average of 4.2% number of LUT savings is achieved on the FPGA. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 54 computer science |
| Programme: | Embedded Systems MSc (60331) |
| Link to this item: | https://purl.utwente.nl/essays/99903 |
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