University of Twente Student Theses
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Mapping dataflow over multiple FPGAs in Clash
Bremmer, D.J. (2020) Mapping dataflow over multiple FPGAs in Clash.
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| Abstract: | This thesis will explain how (Homogenous) Synchronous Dataflow ((H)SDF) graphs can be mapped over multiple FPGAs. This is implemented in Clash, a functional hardware description language that can transform High-level descriptions to low-level synthesizable VHDL, Verilog or SystemVerilog. It has been implemented in such a way that it is deterministic and that over the found implementation, for some examples, a timing analysis is done. So, the desired (H)SDF graph and the implemented one can be studied. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Programme: | Embedded Systems MSc (60331) |
| Link to this item: | https://purl.utwente.nl/essays/85254 |
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